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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DA16200 датащи(PDF) 48 Page - Renesas Technology Corp |
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DA16200 датащи(HTML) 48 Page - Renesas Technology Corp |
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48 / 154 page  DA16200 Ultra Low Power Wi-Fi SoC Datasheet Revision 3.6 04-Jan-2023 CFR0011-120-00 48 of 153 © 2023 Renesas Electronics 7.11 Clock Generator The generation of the system's clocks is described in detail in Figure 22. PLL480M XTAL40M Divide by PLL_CLK_DIV_0_CPU Free running modules HCLK_FR CPU Core (CM4F) BusMatrix Internal SRAM Mask ROM PHY Bus SD/eMMC Divide by CLK_DIV_EMMC Divide by PLL_CLK_DIV_1_XFC QSPI Flash Controller HCLK_XFC 2 nd SPI Host Controller Divide by PLL_CLK_DIV_2_UART UART_0 CLK_UART UART_1 UART_2 Divide by PLL_CLK_DIV_3_OTP OTP CLK_OTP Divide by 2 Divide by PLL_CLK_DIV_5_I2S I2S CLK_I2S I/O PAD Divide by CLK_DIV_I2S Divide by PLL_CLK_DIV_6_AUXA CLK_AUXA Divide by PLL_CLK_DIV_7_C312 CC312 (Security IP) HCLK_CC312 PHY Clock Generator CK EN CG CK EN CG CK EN CG CK EN CG CK EN CG CK EN CG CK EN CG CK EN CG Aux. ADC Divide by CLK_DIV_AUXA Figure 22: Clock Tree Diagram |
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