DA16200 datasheet(119/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

119 of 153

10.5 SPI and I2C Register

DA16200 includes I2C master and slave functions. Four ranges of clock speed are supported:

standard (100 kHz), fast (400 kHz), fast plus (1.0 MHz) and High Speed (3.4 MHz) mode for both

Master and Slave mode.

DA16200 also supports SPI master and Slave functions. To use DA16200 as an SPI master, the

CSB signal can be used with any of the GPIO pins. CSB [3:1] can be selected from the GPIO special

function by setting the registers in the GPIO.

The SPI slave interface is a half-duplexd connection for an external host to control the DA16200. The

range of the SPI clock speed is based on the internal bus clock speed and can be calculated using:

spi clock = system clock/N

where N is an integer divider such as 1,2,3,4,5,6,...

There is a separate communication protocol for SPI slave. See section 9.3 SPI slave for more

detailed information.

Table 180: SPI and I2C Registers Overview

Address

Description

Common control for SPI and I2C Pin Status

0x5008_023C

SPI_INTR_STATUS_REG

SPI Interrupt Status Register

0x5008_0240

SPI_CTRL_REG

SPI Control Register

0x5008_0244

I2C_CTRL_REG

I2C Control Register

0x5008_0248

SPI_LENGTH_REG

SPI Length Register

0x5008_024C

I2C_BUFFER_ADDR_REG

I2C Buffer Address Register

0x5008_0250

SPI_BASE_ADDR_REG

SPI Base Address Register

0x5008_0254

CMD_ADDR_REG

Command Address Register

0x5008_0258

RESP_ADDR1_REG

Response Address1 Register

0x5008_025C

RESP_ADDR2_REG

Response Address2 Register

0x5008_0260

AT_CMD_BASE_REG

AT Command Base Address Register

0x5008_0264

AT_CMD_REF_REG

AT Command Base Address Register

0x5008_0264

SPI_TIMER_REG

SPI Timer Register

Table 181: SPI_INTR_STATUS_REG (0x5008_023C)

Bit

Mode

Symbol

Description

Reset

15:13

R/W

INTR

SPI slave interrupt status register

bit[15]: Command interrupt status/clear

bit[14]: AT Command interrupt status/clear

bit[13]: Processing end interrupt status/clear

0x0

12:0

R/W

Reserved

0x000

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