DA16200 datasheet(74/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

74 of 153

9.10.5

Interrupts

The DA16200 UART block provides five interrupt signals by separate interrupt lines. Each interrupt

conditions are Modem Status, Receive FIFO Request, Transmit FIFO Request, Receive Timeout and

Reception Error. These conditions are logically ORed to provide a single combined interrupt,

UARTINTR. Table 55 shows the interrupt signals.

Table 55: UART Interrupt Signals

Signal Name

Description

UARTMSINTR

UART Modem Status Interrupt

UARTRXINTR

UART Receive FIFO Interrupt

UARTTXINTR

UART Transmit FIFO Interrupt

UARTRTINTR

UART Receive Timeout Interrupt

UARTEINTR

UART Error Interrupt

UARTINTR

UART Interrupt. Five Interrupt signals are combined by OR function

9.10.6

DMA Interface

The DA16200 UART block can generate DMA request signals with register settings by using a DMA

interrupt generator module to connect to DA16200 DMA Controller (DMA1). The DMA operation of

the UART is controlled with the DMA Control Register.

The DA16200 UART provides four DMA signals and receives two DMA signals, two signals to

transmit (TXDMASREQ, TXDMABREQ), which are cleared by a TX clear signal (TXDMACLR) and

two signals to receive (RXDMASREQ, RXDMABREQ), which are cleared by a RX clear signal

(RXDMACLR).

When the DMA interface is not used, the TXDMACLR and RXDMACLR lines should be connected to

a logic 0.

Table 56 shows the pin definition of the UART interface.

Table 56: UART Pin Configuration

Pin Name

Pin Number

I/O

Function Name

QFN

fcCSP

UART0_RXD

M10

UART0_RXD

UART0_TXD

GPIOA7

UART1_RXD

GPIOA5

GPIOA3

GPIOA1

GPIOA6

UART1_TXD

GPIOA4

GPIOA2

GPIOA0

GPIOA5

UART1_CTS

GPIOA4

UART1_RTS

GPIOA11

UART2_RXD

GPIOC7

K12

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