DA16200 datasheet(62/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

62 of 153

AHB

Slave

Control

Registers

Data

Pipe

AHB

Master

Clock

Control

HCLK

HCMD

HDATA[3:0]

CMD/RSP

Pipe

AHB

FIFO

Figure 36: SD/eMMC Block Diagram

Figure 37 shows the timing diagram for the SD/eMMC master.

SD/eMMC_CLK

SD/eMMC_D[3:0]

SD/eMMC_CMD

TCO.DLY

TDO.DLY

TCI.SU

TDI.SU

Figure 37: SD/eMMC Master Timing Diagram

Table 47 lists the timing parameters for the SD/eMMC master.

Table 47: SD/eMMC Master Timing Parameters

Parameter

Symbol

Min

Typ

Max

Unit

SD/eMMC_CLK frequency

FSCLK

MHz

SD/eMMC_CLK clock duty

SD/eMMC_CMD input setup time

TCI.SU

SD/eMMC_CMD output delay time

TCO.DLY

SD/eMMC_D[3:0] input setup time

TDI.SU

SD/eMMC_D[3:0] output delay time

TDO.DLY

9.7

I2S

DA16200 provides an I2S interface. Once an I2S block receives audio data through the DMA, that

audio data is sent to the external port according to the I2S standard. To use the external DAC, output

through the GPIO port is possible when a register setting is made according to the pin configuration

(Table 48).

The I2S also provides a receive function. However, I2S transmission and reception functions cannot

be used at the same time. The transmit and receive functions can be selected by register setting. If

the I2S signal is input from outside after the reception function is set, the audio signal can be

decoded, stored in the FIFO, and read out through the DMA. The decodable reception function

provides 8/16/24/32-bit modes and can receive either mono or stereo.

Using the I2S clock divider register, the internal PLL clock can be variably applied to the I2S clock

source. The available I2S clock source is 24/48 MHz. There is also a way to apply the I2S clock

source directly from outside using the GPIO pin. For accurate I2S audio sampling, the I2S clock

source can be input to external GPIO pins. It needs to select the GPIO pin setting as the I2S clock

input and apply the appropriate clock source. The available I2S clock pins are shown in Table 48.

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