DA16200 datasheet(111/154 Pages) RENESAS

номер детали	DA16200

подробное описание детали	Ultra Low Power Wi-Fi SoC

PDF	154 Pages

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производитель	RENESAS [Renesas Technology Corp]

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

111 of 153

Table 158: HIF_CLK_CNT_CTRL (0x5003_000C)

Bit

Mode

Symbol

Description

Reset

31:23

Reserved

R/W

STOP_HCLK

Enable to Stop SD/eMMC Interface Clock

0: Disable

1: Enable

1'b0

R/W

SYNC_STCTL

Synchronous Circuit Stage Control

0: 3-Stage Synchronizer (Low clock ratio)

1: 2-Stage Synchronizer (High clock ratio)

1'b0

R/W

HCLK_OE

HCLK Output Enable Control

0: Disable

1: Enable (Normal Operation)

1'b1

Reserved

18:17

R/W

HCLK_CTL

Internal Host Clock Control

00: Turn off the internal host clock

01: Turn off the internal host clock immediately

10: Turn on the internal host clock immediately

11: Always turn on internal host clock

2'b11

HCLK_SW

SW Host Clock Control

Note: S/W can program this bit to high/low, to toggle the internal

host clock when HCLK_CTL[1:0] = 2'b00

1'b0

15:0

R/W

HCLK_CT_CNT

Host Clock Control Count Register

This control register specifies the number of host clock to enable

or stop the host clock signal

16'h0

Table 159: HIF_CMD_ARG (0x5003_0010)

Bit

Mode

Symbol

Description

Reset

31:0

R/W

HCLK_CMD_ARG

This register specifies the value of SD/eMMC command

argument

32'h0

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