ST20-GP6 datasheet(105/123 Pages) STMICROELECTRONICS

105 / 123 page

ST20-GP6

105/123

Notes

This is the static speciﬁcation to ensure low current.

Output load of 2mA on all pins except PIO. Output load of 4mA on PIO.

Excludes power used to drive external loads. Includes operation of the 32 KHz watch crys-

tal oscillator.

Device operation suspended by use of the low power controller with

VDD and RTCVDD

within speciﬁcation. Frequency of system clock (fclk) is 16.368 MHz and frequency of low

power clock is 32768 Hz.

With

RTCVDD at 2.4 V and VDD at 0 V. All inputs static except LowPowerClockIn and

LowPowerClockOsc, frequency of low power clock 32768 Hz. All other inputs must be in

the range -0.1 to 0.1 V.

Analogue speciﬁcations

LowPowerClockIn and LowPowerClockOsc analogue pins are dedicated low power pins and

should only be connected as in Figure 13.1 on page 74. Due to their high impedance, they must

not be monitored or loaded by test equipment.

AC speciﬁcations

Notes

The maximum is only a guideline to ensure a low current consumption during the change in

VDD.

The transition need not be monotonic, providing that the

notRST pin is forced low during

the whole period while the main

VDD voltage is not within limits set in the DC operating

conditions.

Symbol

Parameter

Min

Typical

Max

Units

Notes

tvddr

Rise time of

VDD during power up (measured

between 0.3 V and 2.7 V).

5 ns

100 ms

1, 2

tvddf

Fall time of

VDD during power down (measured

between 2.7 V and 0.3 V).

5 ns

100 ms

1, 2

Table 18.4 AC Speciﬁcation

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