ST20-GP6 datasheet(52/123 Pages) STMICROELECTRONICS

номер детали	ST20-GP6

подробное описание детали	GPS PROCESSOR

PDF	123 Pages

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ST20-GP6

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The contents of these addresses can be accessed via

ldtraph, sttraph, ldtrapped and sttrapped

instructions.

8.2

Boot ROM

There is 128K bytes of mask ROM on-chip. This is mapped to the upper 128K of bank 3

(addresses #7FFE0000 to #7FFFFFFF).

If mask ROM is not programmed, internal ROM is disabled and external ROM is used.

When the processor boots from ROM, it jumps to a boot program held in ROM with an entry point 2

bytes from the top of memory at #7FFFFFFE. These 2 bytes are used to encode a negative jump

of up to 256 bytes down in the ROM program. For large ROM programs it may then be necessary

to encode a longer negative jump to reach the start of the routine.

8.3

Internal peripheral space

On-chip peripherals are mapped to addresses in the address range #00000000 to #3FFFFFFF).

They can only be accessed by the device access instructions (see Table 7.19). When used with

addresses in this range, the device instructions access the on-chip peripherals rather than external

memory. For all other addresses the device instructions access memory. Standard load/store

instructions to these addresses will access external memory.

Each on-chip peripheral occupies a 4K block, see the following memory map.

ST20-GP6 датащи(PDF) 52 Page - STMicroelectronics