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ST20-GP6 датащи(PDF) 74 Page - STMicroelectronics |
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ST20-GP6 датащи(HTML) 74 Page - STMicroelectronics |
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74 / 123 page ![]() ST20-GP6 74/123 The SysRatio register, see Table 11.8 on page 69, gives the speed at which the system PLL is running. It contains the relevant PLL multiply ratio when using the PLL, or contains the value ‘1’ when in TimesOneMode for the PLL. 13.3.2 Clocking sources The real time clock and low power timer and alarm must be clocked at all times by one of the following clocking sources: • External clock input ( LowPowerClockIn) — this clock must not be more than one eighth of the system clock rate. In this case the LowPowerClockOsc pin should not be connected on the board. • Watch crystal, as in Figure 13.1. Figure 13.1 Watch crystal clocking source SpeedSelect1 SpeedSelect0 Processor clock speed (MHz) Processor cycle time (ns) approximate Phase lock loop factor (PLLx) 0 0 RESERVED 0 1 16.368 61.1 TimesOneModea a. In TimesOneMode the PLL is disabled to reduce power consumption. 1 0 32.736 30.5 2 1 1 49.104 20.4 3 Table 13.1 Processor speed selection internal low power clock watch crystal LowPowerClockOsc LowPowerClockIn (32768 Hz) GND GND 22 pF 10 pF A B A - this node should have very low capacitance < 10 pF. B - this node must have zero dc load. 330 K Ω |
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