ST20-GP6 datasheet(63/123 Pages) STMICROELECTRONICS

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ST20-GP6

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EMIConﬁgData1Bank0-3

The

EMIConfigData1Bank0-3 registers contain conﬁguration data for each of the EMI banks. The

format of each of the

EMIConfigData1 registers is shown in Table 10.5.

EMIConﬁgData2Bank0-3

The

EMIConfigData2Bank0-3 registers contain conﬁguration data for each of the EMI banks. The

format of each of the

EMIConfigData2 registers is shown in Table 10.6.

EMIConﬁgData1Bank0-3

EMI base address + #04, #14, #24, #34

Read/Write

Bit

Bit ﬁeld

Function

Units

1:0

BEe2TimeRead

Rising edge of

notMemBE. 0 to 3 phases before end of access

cycle

Phases

3:2

BEe1TimeRead

Falling edge of

notMemBE. 0 to 3 phases after start of access cycle Phases

5:4

OEe2TimeRead

Rising edge of

notMemOE. 0 to 3 phases before end of access

cycle

Phases

7:6

OEe1TimeRead

Falling edge of

notMemOE. 0 to 3 phases after start of access cycle Phases

9:8

CEe2TimeRead

Rising edge of

notMemCE. 0 to 3 phases before end of access

cycle

Phases

11:10

CEe1TimeRead

Falling edge of

notMemCE. 0 to 3 phases after start of access cycle Phases

15:12

AccessTimeRead

2 cycles + 0 to 15 cycles

Cycles

Table 10.5

EMIConﬁgData1 register format - 1 per bank

EMIConﬁgData2Bank0-3

EMI base address + #08, #18, #28, #38

Read/Write

Bit

Bit ﬁeld

Function

Units

1:0

BEe2TimeWrite

Rising edge of

notMemBE. 0 to 3 phases before end of access

cycle

Phases

3:2

BEe1TimeWrite

Falling edge of

notMemBE. 0 to 3 phases after start of access cycle Phases

5:4

OEe2TimeWrite

Rising edge of

notMemOE. 0 to 3 phases before end of access

cycle

Phases

7:6

OEe1TimeWrite

Falling edge of

notMemOE. 0 to 3 phases after start of access cycle Phases

9:8

CEe2TimeWrite

Rising edge of

notMemCE. 0 to 3 phases before end of access

cycle

Phases

11:10

CEe1TimeWrite

Falling edge of

notMemCE. 0 to 3 phases after start of access cycle Phases

15:12

AccessTimeWrite

2 cycles + 0 to 15 cycles

Cycles

Table 10.6

EMIConﬁgData2 register format - 1 per bank

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