ST20-GP6 datasheet(38/123 Pages) STMICROELECTRONICS

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ST20-GP6

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InputInterrupts register

The

InputInterrupts register is a read only register. It contains a vector which shows all of the input

interrupts, so bit 0 of the read data corresponds to

InterruptIn0, bit 1 corresponds to InterruptIn1.

Low power controller support registers

The interrupt level controller has 2 additional registers to support the low power controller (see

Chapter 11 on page 66). The external interrupts can be used to provide a wake-up from power-

down mode.

The

IntLPEnable register can be programmed for each interrupt to cause the interrupt to wake-up

the ST20-GP6 from power-down mode. The wake-up occurs when the interrupt goes either high or

low, depending on the setting of the respective bit in the

IntActiveHigh register.

IntLPEnable

The

IntLPEnable register can be set to enable a wake-up from power-down mode when the inter-

rupt occurs.

IntPriority

Interrupt level controller base address + #00 to #1C

Read/Write

Bit

Bit ﬁeld

Function

2:0

IntPriority

Determines the priority of each interrupt input.

IntPriority2:0

Asserts output interrupt

000

0 (lowest priority)

001

010

011

100

101

110

111

7 (highest priority)

Table 6.2

IntPriority register format - 1 register per interrupt

Inputinterrupts

Interrupt level controller base address + #48

Read only

Bit

Bit ﬁeld

Function

1:0

InterruptIn-0

Input interrupt levels.

Table 6.3

InputInterrupts register format

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