ST20-GP6 datasheet(56/123 Pages) STMICROELECTRONICS

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ST20-GP6

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10 Programmable memory interface

The ST20-GP6 programmable memory interface has a 16 bit data bus and provides glueless

support for up to four banks of SRAM memory. Sufﬁcient conﬁguration options are provided to

enable the interface to be used with a wide variety of SRAM speeds, permitting systems to be built

with optimum price/performance trade-offs.

The programmable memory interface is also referred to as the external memory interface (EMI).

The EMI provides conﬁguration information for four independent banks of external memory

devices. The addresses of these bank boundaries are hard wired to give each bank one quarter of

the address space of the machine. Bank 0 occupies the lowest quarter of the [signed] address

space, bank 3 is the highest, see Figure 10.1.

The conﬁguration is held in memory mapped registers within the EMI. Each bank has 64 bits to

hold conﬁguration data. This data is accessed as four 16-bit accesses.

The EMI conﬁguration software ensures that the conﬁguration of a bank is consistent and works

with all devices in the bank before any access to that bank.

Default conﬁgurations on start-up (see “Default conﬁguration” on page 65) allow the slowest

memory to be accessed.

Four conﬁguration control registers (one for each bank) are provided which allow the conﬁguration

data registers to be locked. This prevents an accidental overwrite from destroying the emi

conﬁguration. A conﬁguration status register is also provided to show which banks have been

locked and which banks have been conﬁgured.

The memory map for the conﬁguration registers within the EMI contains 16 x 16-bit data registers

each located at word boundary, plus four lock control registers and a global register for status

information.

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