ST20-GP6 datasheet(83/123 Pages) STMICROELECTRONICS

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ST20-GP6

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Parity may be odd or even, depending on the

ParityOdd bit in the ASCControl register. An even

parity bit will be set, if the modulo-2-sum of the eight data bits is 1. An odd parity bit will be cleared

in this case.

In wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit

(the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and no data will

be transferred.

This feature may be used to control communication in multi-processor systems. When the master

processor wants to transmit a block of data to one of several slaves, it ﬁrst sends out an address

byte which identiﬁes the target slave. An address byte differs from a data byte in that the additional

ninth bit isa1for an address byte and a 0 for a data byte, so no slave will be interrupted by a data

byte. An address byte will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each

slave can examine the 8 least signiﬁcant bits (LSBs) of the received character (the address). The

addressed slave will switch to 9-bit data mode, which enables it to receive the data bytes that will

be coming (with the wake-up bit cleared). The slaves that are not being addressed remain in 8-bit

data + wake-up bit mode, ignoring the following data bytes.

Figure 15.2 9-bit data frames

Transmission

Values to be transmitted are written to the transmit ﬁfo, txﬁfo, by writing to

ASCTxBuffer. The txﬁfo

is implemented as a 16 deep array of 9 bit vectors.

If the ﬁfos are enabled (the

ASCControl(FifoEnable) is set), the txﬁfo is considered full (ASCSta-

tus(TxFull) is set) when it contains 16 characters. Further writes to ASCTxBuffer in this situation

will fail to overwrite the most recent entry in the txﬁfo. If the ﬁfos are disabled, the txﬁfo is consid-

ered full (

ASCStatus(TxFull) is set) when it contains 1 character, and a write to ASCTxBuffer in

this situation will overwrite the contents.

If the ﬁfos are enabled,

ASCStatus(TxHalfEmpty) is set when the txﬁfo contains 8 or fewer char-

acters. If the ﬁfos are disabled, it’s set when the txﬁfo is empty.

Writing anything to

ASCTxReset empties the txﬁfo.

Values are shifted out of the bottom of the txﬁfo into a 9-bit txshift register in order to be transmit-

ted. If the transmitter is idle (the txshift register is empty) and something is written to the

ASCTx-

Buffer so that the txﬁfo becomes non-empty, the txshift register is immediately loaded from the

txﬁfo and transmission of the data in the txshift register begins at the next baud rate tick.

start

bit

9th

bit

(LSB)

1st

stop

bit

2nd

stop

bit

• Data bit (D8)

• Parity bit

• Wake-up bit

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