ST20-GP6 datasheet(62/123 Pages) STMICROELECTRONICS

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ST20-GP6

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10.4 EMI conﬁguration registers

The following is a summary of the conﬁguration registers format. Times are programmed in cycles

or phases: a cycle is one clock cycle, a phase is half a clock cycle.

There are 4 data conﬁguration registers for each of the EMI banks. The base addresses for the EMI

registers is #00002000.

EMIConﬁgData0Bank0-3

The

EMIConfigData0Bank0-3 registers contain conﬁguration data for each of the EMI banks. The

format of each of the

EMIConfigData0 registers is shown in Table 10.3.

EMIConﬁgData0Bank0-3

EMI base address + #00, #10, #20, #30

Read/Write

Bit

Bit ﬁeld

Function

Units

2:0

DeviceType

Device type. Sets the format of the conﬁguration register. This must

be set to 001 on the ST20-GP6.

001 = SRAM/peripheral

4:3

Portsize

Port size

00 = reserved

01 = reserved

10 = 16 bit

11 = 8 bit

6:5

BEactive

notMemBE active, see Table 10.4 below.

8:7

OEactive

notMemOE active, see Table 10.4 below.

10:9

CEactive

notMemCE active, see Table 10.4 below.

12:11

BusReleaseTime

Duration bus release time. 0 to 3 cycles

Cycles

15:13

DataDriveDelay

Drive delay of data bus for writes. 0 to 7 phases

Phases

Table 10.3

EMIConﬁgData0 register format - 1 per bank

CE/OE/BE

ActiveCode

Strobe activity

Inactive

Active during read only

Active during write only

Active during read and write

Table 10.4 Strobe conﬁguration

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