ST20-GP6 datasheet(70/123 Pages) STMICROELECTRONICS

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ST20-GP6

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12 Real time clock and watchdog timer

This chapter speciﬁes the real time clock-calendar (RTC) and watchdog timer (WDT) module for

the ST20-GP6.

The RTC provides a set of continuously running counters which can be used, with suitable soft-

ware, to provide a clock-calendar function. The counter values can be written to set the current

time/data. The RTC is clocked by the 32,768 Hz low power clock input and has a separate power

supply so that it can continue to run when the rest of the chip is powered down.

The WDT provides a fail-safe mechanism to reset the chip if the software fails to clear a counter

within a given period.

12.1 Power supplies

There are two supply voltages to the ST20-GP6, these are: the normal operating supply,

VDD, and

the battery back-up supply,

RTCVDD.

The RTC/WDT and the oscillator are powered by

RTCVDD to enable the RTC contents to be main-

tained at minimal power consumption.

12.2 Real time clock

The RTC contains two counters: a 30 bit milliseconds counter and a 16 bit weeks counter. This

allows large time values to be represented to high accuracy.

These counters are not reset as the RTC must run continuously.

12.2.1 RTC counters

The milliseconds counter increments at 1.024KHz. Thus, the value does not actually represent mil-

liseconds — this must be taken into account by any software using it. The milliseconds counter is

modulo the number of milliseconds in 1 week, or 619,315,200 — i.e. 1024 (one second) X 60 (one

minute) X 60 (one hour) X 24 (one day) X 7 (one week).

The weeks counter is incremented when the milliseconds counter wraps around from 619,315,199

to 0. This is a 16 bit counter; the GPS epoch is only deﬁned up to 210 weeks, so having extra bits

here allows the system to handle times later than this.

The current value of both counters can be read at any time by the CPU, but care must be taken to

handle the end of week carry occurring between two reads.

12.3 Watchdog timer

The WDT has a counter, clocked to give a nominal 2 second delay. This counter is periodically

cleared, under software control, as described below. If the software fails to clear the counter within

the 2 second period then a watchdog reset signal (

notWdReset) is generated to reset the chip.

A status ﬂag is set by a watchdog reset. This can be used to indicate to application code that the

system was reset by the watchdog timer. This status bit is reset

only by the

notRST input to the

chip.

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