ST20-GP6 datasheet(64/123 Pages) STMICROELECTRONICS

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ST20-GP6

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EMIConﬁgData3Bank0-3

The

EMIConfigData2Bank0-3 registers contain conﬁguration data for each of the EMI banks. The

format of each of the

EMIConfigData3 registers is shown in Table 10.7.

EMIConfigLockBank0-3 registers

The

EMIConfigLockBank0-3 registers (one for each bank) allow the conﬁguration data registers

to be locked. This prevents an accidental overwrite from destroying the emi conﬁguration.

A system reset clears these registers.

EMIConfigStatus register

The

EMIConfigStatus register is provided to indicate which registers have been written to and the

status of the lock bits. Table 10.9 shows the format of the

EMIConfigStatus register.

EMIConﬁgData3Bank0-3

EMI base address + #0C, #1C, #2C, #3C

Read/Write

Bit

Bit ﬁeld

Function

LatchPoint

Position of latch point in cycle.

0 = 1 cycle before end of access cycle

1 = end of access cycle

15:1

Reserved, write 0.

Table 10.7

EMIConﬁgData3 register format - 1 per bank

EMIConﬁgLockBank0-3

EMI base address + #40, #44, #48, #4C

Write only

Bit

Bit field

Function

ConﬁgLock

Write protection bit. When set,

EMIConﬁgData0-3 for the bank is read only.

Table 10.8

EMIConfigLock register format - 1 per bank

EMIConﬁgStatus

EMI base address + #50

Read only

Bit

Bit field

Function

WrittenBank0

Bank 0 conﬁguration data registers have been written to.

WrittenBank1

Bank 1conﬁguration data registers have been written to.

WrittenBank2

Bank 2 conﬁguration data registers have been written to.

WrittenBank3

Bank 3 conﬁguration data registers have been written to.

WriteLockBank0 EMIConﬁgData0-3Bank0 registers are write protected.

WriteLockBank1 EMIConﬁgData0-3Bank1 registers are write protected.

WriteLockBank2 EMIConﬁgData0-3Bank2 registers are write protected.

WriteLockBank3 EMIConﬁgData0-3Bank3 registers are write protected.

Table 10.9

EMIConfigStatus register format

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