ST20-GP6 datasheet(31/123 Pages) STMICROELECTRONICS

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ST20-GP6

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Interrupts on the ST20-GP6 are implemented via an on-chip interrupt controller peripheral. An

interrupt can be signalled to the controller by one of the following:

•

a signal on an external

Interrupt pin

•

a signal from an internal peripheral or subsystem

•

software asserting an interrupt in the

Pending register

5.1

Interrupt vector table

The interrupt controller contains a table of pointers to interrupt handlers. Each interrupt handler is

represented by its workspace pointer (

Wptr). The table contains a workspace pointer for each level

of interrupt.

The

Wptr gives access to the code, data and interrupt save space of the interrupt handler. The

position of the

Wptr in the interrupt table implies the priority of the interrupt.

Run-time library support is provided for setting and programming the vector table.

5.2

Interrupt handlers

At any interruptible point in its execution the CPU can receive an interrupt request from the inter-

rupt controller. The CPU immediately acknowledges the request.

In response to receiving an interrupt the CPU performs a procedure call to the process in the vec-

tor table. The state of the interrupted process is stored in the workspace of the interrupt handler as

shown in Figure 5.2. Each interrupt level has its own workspace.

Figure 5.2 State of interrupted process

Before interrupt

Wptr

Areg

Breg

Creg

Interrupting high priority

Wptr

Iptr

Status

Wptr

Null Status

process

Interrupting low priority

process or CPU idle

Handler

Iptr

Handler

Status

Handler

Iptr

Handler

Status

Handler

Iptr

Handler

Status

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