ST20-GP6 datasheet(6/123 Pages) STMICROELECTRONICS

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ST20-GP6

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The ST20-GP6 can implement the GPS digital signal processing algorithms using less than 50% of

the available CPU processing power. This leaves the rest available for integrating OEM application

functions such as route-ﬁnding, map display and telemetry. A hardware microkernel in the ST20

CPU supports the sharing of CPU time between tasks without an operating system or executive

overhead.

The architecture is based on the ST20 CPU core and supporting macrocells developed by

STMicroelectronics. The ST20 micro-core family provides the tools and building blocks to enable

the development of highly integrated application speciﬁc 32-bit devices at the lowest cost and

fastest time to market. The ST20 macrocell library includes the ST20Cx family of 32-bit VL-RISC

(variable length reduced instruction set computer) micro-cores, embedded memories, standard

peripherals, I/O, controllers and ASICs.

The ST20-GP6 uses the ST20 macrocell library to provide the hardware modules required in a

GPS system. These include:

•

DSP hardware

•

Dual channel UART for serial communications

•

Two parallel I/O modules providing 16 bits of parallel I/O

•

Interrupt controller

•

Real time clock/calendar and watchdog timer

•

128 Kbytes of on-chip ROM for application code

•

64 Kbytes of on-chip RAM, of which 16 Kbytes is battery backed

•

Diagnostic control unit and test access port for development support

The ST20-GP6 is supported by a range of software and hardware development tools for PC and

UNIX hosts including an ANSI-C ST20 software toolset and the ST20 INQUEST window based

debugging toolkit.

ST20-GP6 датащи(PDF) 6 Page - STMicroelectronics