ST20-GP6 datasheet(16/123 Pages) STMICROELECTRONICS

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ST20-GP6

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PRNinitialVal0-1 register, see Table 3.8. If uninitialized by the software, the PRNinitialVal register

defaults to 11 1111 1111 (#3FF) as required for GPS satellites.

The

PRNcode0-11 and PRNinitialVal0-1 registers are normally written only when the satellite is

ﬁrst chosen.

PRNphase0-11 registers

The

PRN0-11phase registers determine the relative delay between the receiver master clock, and

the start of the one millisecond repetitive code sequence. The code sequence starts when the

receiver clock counter (invisible to the software except through message timestamps) reaches the

value written to the

PRNphase0-11 register. The PRNphase0-11 register must only be written

once per satellite milliseconds-epoch, which varies from the receiver epoch dynamically due to sat-

ellite motion. Synchronism with the software is achieved by reading the register, when a write

enable ﬂag is returned. If not enabled, the write operation is abandoned by the software.

The 19-bit value comprises three ﬁelds. The 3 least signiﬁcant bits represent the fractional-delay in

eighths of a code-chip. The middle 10 bits represent the integer delay in code-chips, 0-1022, with

the value 1023 illegal. The upper 6 most signiﬁcant bits represent the delay in integer milliseconds.

Note also that the eighth-chip resolution of the code generator is not sufﬁcient for positioning. At

125 ns it represents approximately 40 m of range, over 100 m of position. The software must main-

tain the range measurements around the 1 ns resolution level in a 32-bit ﬁeld, and send an appro-

priate 19-bit sub-ﬁeld to the register. Note, care must be taken when calculating this ﬁeld from a

computed delay, or vice versa, to allow for the missing value 1023. The overall register bit-ﬁeld can-

not be used mathematically as a single binary number.

PRNphase0-11WrEn registers

The

PRNphase0-11WrEn ﬂags are active low ﬂags that record when the PRNphase0-11 register

can be updated. The

PRNphaseWrEn ﬂag for a channel is set high when the corresponding PRN-

phase register is written. The ﬂag is reset again when the value written is loaded into the PRN gen-

PRNphase0-11

DSP base address + #40 to #6C

Write only

Bit

Bit ﬁeld

Function

2:0

FractionalDelay

Fractional delay in eighths of a code-chip.

12:3

IntegerDelay

Integer delay in code-chips. Value 0-1022. Note, the value 1023 is illegal.

18:13

Delay

Delay in integer milliseconds.

Table 3.4

PRNphase0-11 register format

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