ST20-GP6 datasheet(73/123 Pages) STMICROELECTRONICS

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ST20-GP6

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13 System services

The system services module includes the control system, the PLL and power control. System

services include all the necessary logic to initialize and sustain operation of the device.

13.1 Reset, initialization and debug

The ST20-GP6 is controlled by a

notRST pin which is a global power-on-reset.

13.1.1 Power-on reset

notRST initializes the device and causes it to enter its boot sequence (see Section 13.2 on

bootstrap).

notRST must be asserted at power-on and held for 10 ms (or at least 8

LowPowerClockIn cycles) after both Vdd is in range and ClockIn is stable.

When

notRST is asserted low, all modules are forced into their power-on reset condition. The

clocks are stopped. The rising edge of

notRST is internally synchronized before starting the

initialization sequence.

13.2 Bootstrap

The ST20-GP6 can be bootstrapped from external ROM or internal ROM. When booting from

ROM, the ST20-GP6 starts to execute code from the top two bytes in external memory, at address

#7FFFFFFE which should contain a backward jump to a program in ROM.

13.3 Clocks

An on-chip phase locked loop (PLL) generates all the internal high frequency clocks. The PLL is

used to generate the internal clock frequencies needed for the CPU. Alternatively a direct clock

input can provide the system clocks.

The internal clock may be turned off (including the PLL) enabling power down mode.

The ST20-GP6 can be set to operate in

TimesOneMode, which is when the PLL is bypassed. Dur-

ing

TimesOneMode the input clock must be in the range 0 to 30 MHz and should be nominally 50/

50 mark space ratio.

Note, the single clock input (

ClockIn) must be 16.368 MHz for correct GPS operation.

13.3.1 Speed select

The speed of the internal processor clock is variable in discrete steps. The clock rate at which the

ST20-GP6 runs is determined by the logic levels applied on the two speed select lines

SpeedSelect0-1 as detailed in Table 13.1. The frequency of ClockIn (fclk) for the speeds given in

the table is 16.368 MHz.

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