ST20-GP6 datasheet(34/123 Pages) STMICROELECTRONICS

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ST20-GP6

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TriggerMode register

Each interrupt channel can be programmed to trigger on rising/falling edges or high/low levels on

the external

Interrupt.

Note, level triggering is different to edge triggering in that if the input is held at the triggering level, a

continuous stream of interrupts is generated.

Mask register

An interrupt mask register is provided in the interrupt controller to selectively enable or disable

external interrupts. This mask register also includes a global interrupt disable bit to disable all

external interrupts whatever the state of the individual interrupt mask bits.

To complement this the interrupt controller also includes an interrupt pending register which con-

tains a pending ﬂag for each interrupt channel. The

Mask register performs a masking function on

the

Pending register to give control over what is allowed to interrupt the CPU while retaining the

ability to continually monitor external interrupts.

On start-up, the

Mask register is initialized to zeros, thus all interrupts are disabled, both globally

and individually. Whena1iswritten to the

GlobalEnable bit, the individual interrupt bits are still

disabled and must also have a 1 individually written to the

InterruptEnable bit to enable the

respective interrupt.

The

Mask register is mapped onto two additional addresses so that bits can be set or cleared indi-

vidually.

TriggerMode

Interrupt controller base address + #40 to #5C

Read/Write

Bit

Bit ﬁeld

Function

2:0

Trigger

Control the triggering condition of the

Interrupt, as follows:

Trigger2:0

Interrupt triggers on

000

No trigger mode

001

High level - triggered while input high

010

Low level - triggered while input low

011

Rising edge - low to high transition

100

Falling edge - high to low transition

101

Any edge - triggered on rising and falling edges

110

No trigger mode

111

No trigger mode

Table 5.2

TriggerMode register format - one register per interrupt

Mask

Interrupt controller base address + #C0

Read/Write

Bit

Bit ﬁeld

Function

7:0

Interrupt7:0Enable

When set to 1, interrupt is enabled. When 0, interrupt is disabled.

GlobalEnable

When set to 1, the setting of the interrupt is determined by the speciﬁc

InterruptEnable bit. When 0, all interrupts are disabled.

15:8

Reserved, write 0.

Table 5.3

Mask register format

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