ST20-GP6 datasheet(10/123 Pages) STMICROELECTRONICS

10 / 123 page

ST20-GP6

10/123

•

Power to most of the chip removed — only the real time clock supply (

RTCVDD) power on.

In power-down mode the processor and all peripherals are stopped, including the external memory

controller and optionally the PLL. Effectively the internal clock is stopped and functional operation

is stalled. On restart the clock is restarted and the chip resumes normal functional operation.

Serial communications

The

ST20-GP6

has

two

UARTs

(Asynchronous

Serial

Controllers

(ASCs))

for

serial

communication. The UARTs provide an asynchronous serial interface and can be programmed to

support a range of baud rates and data formats, for example, data size, stop bits and parity.

Interrupt subsystem

The ST20-GP6 interrupt subsystem supports eight prioritized interrupts. Four interrupts are

connected to on-chip peripherals (2 for the UARTs, 2 for the programmable IO), two are available

as external interrupt pins and two are spare.

Each interrupt level has a higher priority than the previous and each level supports only one

software handler process.

Note that interrupt handlers must not prevent the GPS DSP data trafﬁc from being handled. During

continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has

a 32

µs rate and thus all interrupts must be disabled except if used to stop GPS operation.

Parallel IO module

Sixteen bits of parallel IO are provided. Each bit is programmable as an output or an input. Edge

detection logic is provided which can generate an interrupt on any change of an input bit.

JTAG Test Access Port

The Test Access Port (TAP) supports the IEEE 1149.1 JTAG test standard.

Diagnostic controller

The diagnostic controller is a programmable module which connects directly into the CPU. It can be

accessed by the TAP. This allows debugging systems to be used which do not affect CPU

performance or intrude into application code. Debugging support includes:

•

hardware breakpoint and watchpoint

•

real time trace

•

external LSA triggering support

It is also used to provide system services, including booting the CPU.

System services module

The ST20-GP6 system services module includes:

•

reset and initialization port.

•

phase locked loop (PLL) — accepts 16.368 MHz input and generates all the internal high

frequency clocks needed for the CPU.

ST20-GP6 датащи(PDF) 10 Page - STMicroelectronics

ST20-GP6 датащи(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL