ST20-GP6 datasheet(30/123 Pages) STMICROELECTRONICS

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ST20-GP6

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Interrupt controller

The ST20-GP6 supports external interrupts, enabling an on-chip subsystem or external interrupt

pin to interrupt the currently running process in order to run an interrupt handling process

The ST20-GP6 interrupt subsystem supports eight prioritized interrupts. This allows nested pre-

emptive interrupts for real-time system design. In addition, there is an interrupt level controller

(refer to Chapter 6) which multiplexes incoming interrupts onto the eight programmable interrupt

levels. This multiplexing is controllable by software. There are 6 sources of interrupts. Four of these

are internal (2 for the UARTs, 2 for the programmable IO) and two are external.

All interrupts are a higher priority than the low priority process queue. Each interrupt can be pro-

grammed to be at a lower priority or a higher priority than the high priority process queue, this is

determined by the

Priority bit in the HandlerWptr0-7 registers, see Table 5.1 on page 33.

Note: Interrupts (

Interrupt0-7) which are speciﬁed as higher priority must be contiguous from the

highest numbered interrupt downwards, i.e. if 4 interrupts are programmed as higher priority and 4

as lower priority the higher priority interrupts must be

Interrupt7:4 and the lower priority interrupts

Interrupt3:0.

Note that interrupt handlers must not prevent the GPS DSP data trafﬁc from being handled. During

continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has

a32

µs rate and thus care must be taken with interrupt priorities unless used to stop GPS opera-

tion.

Figure 5.1 Interrupt priority

Interrupt 7

Interrupt 0

High priority

Low priority

Increasing

pre-emption

process

Interrupt 7

Interrupt 0

when Priority bit set to 1

when Priority bit set to 0

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