ST20-GP6 datasheet(24/123 Pages) STMICROELECTRONICS

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ST20-GP6

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ldclock (load clock), stclock (store clock) instructions allow total control over the clock value and the

clockenb (clock enable), clockdis (clock disable) instructions allow each clock to be individually

stopped and re-started.

Figure 4.3 shows two processes waiting on the timer queue, one waiting for time 21, the other for

time 31.

Figure 4.3 Timer registers

4.6

Traps and exceptions

A software error, such as arithmetic overﬂow or array bounds violation, can cause an error ﬂag to

be set in the CPU. The ﬂag is directly connected to the

ErrorOut pin. Both the ﬂag and the pin can

be ignored, or the CPU stopped. Stopping the CPU on an error means that the error cannot cause

further corruption. As well as containing the error in this way it is possible to determine the state of

the CPU and its memory at the time the error occurred. This is particularly useful for postmortem

debugging where the debugger can be used to examine the state and history of the processor

leading up to and causing the error condition.

In addition, if a trap handler process is installed, a variety of traps/exceptions can be trapped and

handled by software. A user supplied trap handler routine can be provided for each high/low pro-

cess priority level. The handler is started when a trap occurs and is given the reason for the trap.

The trap handler is not re-entrant and must not cause a trap itself within the same group. All traps

can be individually masked.

4.6.1 Trap groups

The trap mechanism is arranged on a per priority basis. For each priority there is a handler for each

group of traps, as shown in Figure 4.4.

ClockReg0

TnextReg0

TptrReg0

Work spaces

Program

Empty

Comparator

Alarm

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