ST20-GP6 datasheet(72/123 Pages) STMICROELECTRONICS

72 / 123 page

ST20-GP6

72/123

that an update of the registers is in progress. A new value must not be written to the RTC counters

until this status bit clears (up to two RTC clock cycles later).

WDTclear registers

The watchdog counter is cleared by writing to two registers (

WDTclearA and WDTclearB regis-

ters). Each of these must have the correct values (0xA and 0x5, respectively) written to them in

either order to clear the counter.

WDTstatus register

The

WDTstatus register can be read to determine if the device was reset by the notRST input or

by a watchdog time-out. This status bit is reset

only by the

notRST input to the chip.

RTCstatus

RTC/WDT base address + #08

Read

Bit

Bit ﬁeld

Function

RESERVED

Always returns 0.

Indicates whether an update of the registers is in progress.

0 = RTCweeks and RTCmilliseconds registers can be written;

1 = RTC update in progress. RTCweeks and RTCmilliseconds registers

cannot be

written

Table 12.4

RTCstatus register format

WDTclearA

RTC/WDT base address + #10

Write

Bit

Bit ﬁeld

Function

3:0

WDTclearA

First WDT clear address. Write 0xA.

Table 12.5

WDTclearA register format

WDTclearB

RTC/WDT base address + #14

Write

Bit

Bit ﬁeld

Function

3:0

WDTclearB

Second WDT clear address. Write 0x5.

Table 12.6

WDTclearB register format

WDTstatus

RTC/WDT base address + #18

Read

Bit

Bit ﬁeld

Function

WDTstatus

Watchdog timer status ﬂag.

0 = chip reset normally (by an external

notRST)

1 = chip reset by watchdog timer

Table 12.7

WDTstatus register format

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