MSP430 datasheet(29/88 Pages) TI

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7.3.1.6 DAC Register Structure and CLEAR State

The AFE88101 DAC has a 16-bit voltage output, and the AFE78101 DAC has a 14-bit voltage output. Table

7-1 shows four possible VOUT DAC output ranges. With a voltage-to-current converter stage, the narrow range

corresponds to a 4-mA to 20-mA range. The full range allows for undercurrents and overcurrents from 3 mA to

25 mA, and is controlled by DAC_CFG.RANGE.

The AFEx8101 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register

without writing to the DAC_DATA register, referred to as the CLEAR state. Setting the DAC to CLEAR state also

sets the DAC output range according to DAC_CFG.CLR_RANGE. For register details, see Table 7-15.

Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled,

the output slews during the transition. Figure 7-7 shows the full AFEx8101 DAC_DATA signal path. The devices

synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs)

with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET

values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY.

Set the DAC to CLEAR state either by:

1. Setting DAC_CFG.CLR.

2. Configuring the DAC to transition to the CLEAR state in response to an alarm condition.

3. Using the SDI pin in UBM or the SCLR pin in SPI mode as the CLEAR state input pin.

Method 1 is a direct command to the AFEx8101 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to

1h to set the DAC to CLEAR state.

Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to

use this method, see Table 7-24 and Section 7.3.3.1.

Method 3 supports setting the DAC to CLEAR state without writing to the AFEx8101. This pin-based DAC

CLEAR state function is available in SPI mode on the SCLR pin, or in UBM on the SDI pin. The SCLR pin must

be tied to GND in UBM. For details of connection options based on communication modes and pins used in each

mode, see Section 7.5.1. Set the appropriate pin high to drive the DAC to CLEAR state.

DAC_DATA

DAC_CLR_CODE

DAC_CFG.CLR Register 03h (Method 1)

ALARM_ACT Register 10h (Method 2)

Clear Input Pin (Method 3)

DAC_GAIN

DAC_OFFSET

DAC_CODE

DAC_CFG.SR_MODE

DAC_CFG.SR_STEP

DAC_CFG.SR_CLK

DAC_OUT

Slew Rate: Mode, Step

Size, and Clock Timing

DAC_CFG.SR_EN

Slew Enable

Figure 7-7. DAC Data Path

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AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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