MSP430 datasheet(40/88 Pages) TI

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7.3.3.6 Fault Detection

There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the

assertion and deassertion of alarm conditions for all the ADC channels.

ADC_CFG.FLT_CNT determines the number of consecutive failures needed to trip an alarm condition. For

example, if ADC_CFG.FLT_CNT is set for three counts, then three consecutive conversions must be outside

of the thresholds. Each failure counts towards the FLT_CNT limit even if the failures alternate between high

threshold and low threshold.

ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the

hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis

is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the

threshold value.

Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls

outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that

channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold,

respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only

eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to

0xF, and the low thresholds four LSBs are hardcoded to 0x0.

All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main

DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. Table 7-7 shows the calculations

used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most

columns are determined by the threshold columns to the left and given some margin. The four LSBs are

assigned as described previously.

Table 7-7. Self Diagnostic (SD) Alarm ADC Thresholds

ADC

INPUT

ACCEPTED LOW

VALUE

ACCEPTED HIGH

VALUE

LOW

THRESHOLD

HIGH

THRESHOLD

ADC LOW (HEX) ADC HIGH (HEX)

SD0

VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV

0.54375 V

0.70625 V

0x6D0

0x92F

SD1

PVDD/6

1.65/6 – 25 mV

6/6 + 25 mV

0.25 V

1.025 V

0x310

0xD3F

SD2

VDD/2

1.6/2 – 25 mV

2/2 + 25 mV

0.775 V

1.025 V

0x9C0

0xD3F

SD3

0.6 V

0.6 V – 9% – 25 mV

0.6 V + 9% + 25 mV

0.521 V

0.679 V

0x690

0x8CF

SD4

VOUT/2

VOUT/2 – 6 mV

VOUT/2 + 6 mV

VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040

The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code.

The threshold is different for each DAC range and is adjusted accordingly. Equation 9 shows the expected ADC

code for RANGE = 0, and Equation 10 shows the expected ADC code for RANGE = 1.

ADCExpectedCode:RANGE0= DAC_CODEMSB:MSB–11×113÷128 +492

(9)

ADCExpectedCode:RANGE1= DAC_CODEMSB:MSB–11×82÷128 +655

(10)

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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