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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSP430 датащи(PDF) 52 Page - Texas Instruments |
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MSP430 датащи(HTML) 52 Page - Texas Instruments |
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52 / 88 page  7.6 Register Maps Table 7-10 lists the memory-mapped registers for the AFEx8101 registers. Consider all register offset addresses not listed in Table 7-10 as reserved locations; do not modify these register contents. Table 7-10. Register Map ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h NOP NOP [15:0] 01h DAC_DATA DATA [15:0] 02h CONFIG RESERVED CRC_ERR_CNT [1:0] CLKO_DIV CLKO_EN RESERVED UBM_ IRQ_EN IRQ_ PIN_EN CLR_ PIN_EN UART_DIS RESERVED CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR CLR_ RANGE RANGE 04h DAC_GAIN GAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 06h DAC_CLR_ CODE CODE [15:0] 07h RESET RESERVED SW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_ RANGE EOC_ PER_CH CONV_RATE [1:0] DIRECT_ MODE 09h ADC_INDEX_ CFG RESERVED STOP [3:0] START [3:0] 0Ah TRIGGER RESERVED SHADOW LOAD ADC 0Bh SPECIAL_ CFG (1) RESERVED OTP_ LOAD_ SW_RST ALMV_ POL AIN1_ENB 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 12h AIN0_ THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_ THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_ THRESHOLD Hi [7:0] Lo [7:0] 16h UBM (2) RESERVED REG_ MODE 1Dh ALARM_ STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_ CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_ AIN1_FLT ADC_ AIN0_FLT ADC_ TEMP_ FLT THERM_ ERR_FLT THERM_ WARN_ FLT 1Eh GEN_ STATUS_MASK RESERVED SR_ BUSYn ADC_ EOC RESERVED BREAK_ FRAME_ ERR BREAK_ PARITY_ ERR UART_ FRAME_ ERR UART_ PARITY_ ERR 20h ALARM_ STATUS GEN_ IRQ RESERVED SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_ LOADEDn OTP_ CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_ AIN1_FLT ADC_ AIN0_FLT ADC_ TEMP_ FLT THERM_ ERR_FLT THERM_ WARN_ FLT 21h GEN_ STATUS ALARM_ IRQ RESERVED OTP_ BUSY RESERVED RESET SR_ BUSYn ADC_ EOC ADC_ BUSY PVDD_HI BREAK_ FRAME_ ERR BREAK_ PARITY_ ERR UART _FRAME _ERR UART_ PARITY_ ERR AFE78101, AFE88101 SLASF21 – DECEMBER 2022 www.ti.com 52 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AFE78101 AFE88101 |
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