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7.5 Programming

The AFEx8101 communicate with the system controller through a serial interface that supports either a UART-

compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can

be enabled. Figure 7-17 and Figure 7-18 show the configurations to enable SPI mode and UART break mode

(UBM), respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be

disabled by the user. UBM does not support CRC, but does support the UART protocol parity bit.

7.5.1 Communication Setup

After any reset or power up, the AFEx8101 wake up able to use the SPI or UART break mode (UBM). The

devices include a robust mechanism that configures the interface between either an SPI-compatible or UART-

compatible protocol based system, thus preventing protocol change during normal operation. The selection is

based on initial conditions from the respective hardware configurations (see Figure 7-17 and Figure 7-18) and

any subsequent user configuration.

7.5.1.1 SPI Mode

By default, the AFEx8101 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in

SPI mode:

1. Set CONFIG.UART_DIS = 1 (disables the UART communication).

2. Optionally, set CONFIG.DSDO, CONFIG.FSDO, CONFIG.CLR_PIN_EN, and CONFIG.IRQ_PIN_EN. For

details, see Table 7-14.

IOVDD

UART

(UBM)

Control Logic

SDI

SDO

SCLK

UARTOUT

UARTIN

Clock

Data In

Data Out

Chip Select

System

Controller

AFE

Minimum

Functionality

IOVDD

RESET

SCLR

UART

(UBM)

Control Logic

SDI

SDO

SCLK

UARTOUT

UARTIN

Clock

Data In

Data Out

Chip Select

Reset

Interrupt

System

Controller

AFE

Maximum

Functionality

RESET

SCLR

Clear

GND

IOVDD

CLK_OUT

Monitor

Figure 7-17. SPI Mode Connections

Figure 7-17 shows the SPI mode logical connections (through the isolation barrier, if used) for both

minimum functionality (all optional pins disconnected) and maximum functionality (all pins connected). If

CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set

CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If

the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read

request.

7.5.1.2 UART Mode

At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and

the register must be set again to use UBM. To set up the device in UBM:

1. Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device

and enables the UART interface access to the entire register map.

2. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See Table 7-14 for details).

Figure 7-18 shows the UBM logical connections (through the isolation barrier, if used) for both

minimum functionality (all optional pins disconnected) and maximum functionality (all pins connected). If

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SLASF21 – DECEMBER 2022

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