MSP430 datasheet(61/88 Pages) TI

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7.6.1.14 WDT Register (Offset = 11h) [Reset = 0018h]

Return to the Register Map.

Table 7-25. WDT Register Field Descriptions

Bit

Field

Type

Reset

Description

15-6

RESERVED

5-3

WDT_UP

R/W

Watchdog Timer (WDT) Upper Limit

If the WDT is enabled and the timer exceeds the programmed value,

a WDT error is asserted. All times are based on 1200-Hz clock

(1.2288 MHz / 1024).

0h = 53 ms (64 clocks)

1h = 106 ms (128 clocks)

2h = 427 ms (512 clocks)

3h = 853 ms (1024 clocks, default)

4h = 1.7 s (2048 clocks)

5h = 2.56 s (3072 clocks)

6h = 3.41 s (4096 clocks)

7h = 5.12 s (6144 clocks)

2-1

WDT_LO

R/W

WDT Lower Limit

If the WDT is enabled and the WDT Lower Limit is enabled, then

only a write to this register resets the WDT timer. If the write occurs

before the WDT Lower Limit time, or after the WDT Upper Limit

time, then a WDT error is asserted. If WDT Lower Limit is disabled,

then a write to any register resets the timer. This is true for both

SPI and UART Break modes. All times are based on 1200-Hz clock

(1.2288 MHz / 1024).

0h = Disabled (default)

1h = 53 ms (64 clocks)

2h = 106 ms (128 clocks)

3h = 427 ms (512 clocks)

WDT_EN

R/W

WDT Enable

0h = Disabled (default); 1h = Enabled

7.6.1.15 AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h]

Return to the Register Map.

Table 7-26. AIN0_THRESHOLD Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

R/W

FFh

High Threshold for Channel AIN0 {[11:4],4b1111}

This value is compared (>) against AIN0 data bits[11:0].

7-0

R/W

Low Threshold for Channel AIN0 {[11:4],4b0000}

This value is compared (<) against AIN0 data bits[11:0].

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SLASF21 – DECEMBER 2022

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