MSP430 datasheet(71/88 Pages) TI

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The AFEx8101 are extremely low-power 16-bit and 14-bit voltage output DACs. The DACs support a low output

range of 0.15 V to 1.25 V or a high output range of 0.3 V to 2.5 V. These devices have an onboard oscillator

and an optional precision internal reference. Use these output values with a voltage-to-current (V-to-I) converter

stage for 4-mA to 20-mA, loop-powered applications. These devices also feature a SAR ADC that is used to

measure internal and external nodes for making diagnostic measurements with fault detection and alarm actions.

Use these diagnostic measurements together with the CRC and watchdog timer monitoring for device and

system monitoring for functional safety.

The AFEx8101 can operate using extremely low power with 1.8-V supplies. For low-voltage operation, use

PVDD with a 1.8-V nominal supply and an operating range of 1.71 V to 1.89 V. Run the digital interface supply,

IOVDD, from 1.71 V to 5.5 V. During low-voltage operation, the VDD LDO is automatically disabled and VDD

is tied to PVDD. Low-voltage operation allows for both lower power for field transmitter applications and better

voltage compliance when there are high resistances in the loop.

With higher-supply operation, the PVDD has an operating range of 2.7 V to 5.5 V. With this range of operation,

the VDD is powered from an onboard LDO.

8.1.1 Multichannel Configuration

Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS

signals are required from the microcontroller for all the AFEx8101 devices in the system. The SDI, SDO, and

SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the

number of microcontroller GPIO signals required for communication, as well as the number of isolation channels

for isolated systems. The multichannel configuration block diagram is shown in Figure 8-1.

Microcontroller

AFE #1

GPIO1

SCLK

DOUT

DIN

AFE #2

AFE #3

GPIO2

GPIO3

ALARM

SCLK

SDI

SDO

ALARM

SCLK

SDI

SDO

ALARM

SCLK

SDI

SDO

ALARM

Figure 8-1. Multichannel Configuration

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AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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