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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSP430 датащи(PDF) 3 Page - Texas Instruments |
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MSP430 датащи(HTML) 3 Page - Texas Instruments |
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3 / 88 page  5 Pin Configuration and Functions 1 UARTIN 1 UARTIN 18 VOUT 18 VOUT 2 UARTOUT 2 UARTOUT 17 PVDD 17 PVDD 3 NC 3 NC 16 POL_SEL/AIN1 16 POL_SEL/AIN1 4 SCLR 4 SCLR 15 AIN0 15 AIN0 5 REF_EN 5 REF_EN 14 GND 14 GND 6 RESET 6 RESET 13 VDD 13 VDD Not to scale Not to scale 1 UARTIN 18 VOUT 2 UARTOUT 17 PVDD 3 NC 16 POL_SEL/AIN1 4 SCLR 15 AIN0 5 REF_EN 14 GND 6 RESET 13 VDD Not to scale Figure 5-1. RRU (24-pin UQFN) Package, Top View Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. AIN0 15 AI ADC input voltage. The input range is 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V. ALARM 24 DO Alarm notification. Open drain. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). CLK_OUT 11 DO Clock output. This pin can be configured as a clock output for the 1.2288 ‑MHz internal clock. CS 10 DI SPI chip-select. Data bits are clocked into the serial shift register when CS is logic low. When CS is logic high, SDO is in a high-impedance state and data on SDI are ignored. Do not leave any digital input pins floating. GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GND 21, 22 P Digital and analog ground. IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. NC 3, 23 – No connection. Leave floating. POL_SEL/AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input, and VOUT DAC output. When 2.7 V to 5.5 V is provided, the internal LDO turns on and drives VDD internally. When 1.71 V to 1.89 V is provided, the internal LDO is disabled. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. RESET 6 DI Reset. Logic low on this pin places the device into power-down mode and resets the device. Logic high returns the device to normal operation. Do not leave any digital input pins floating. www.ti.com AFE78101, AFE88101 SLASF21 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: AFE78101 AFE88101 |
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