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MSP430 датащи(PDF) 10 Page - Texas Instruments |
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MSP430 датащи(HTML) 10 Page - Texas Instruments |
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10 / 88 page ![]() 6.6 Timing Requirements all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2, 2.7 V ≤ PVDD ≤ 5.5 V, VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V, and TA = –40°C to +125°C (unless otherwise noted) PARAMETER MIN NOM MAX UNIT SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz tSCLKHIGH SCLK high time 36 ns tSCLKLOW SCLK low time 36 ns tCSHIGH CS high time 80 ns tCSS CS to SCLK falling edge setup time 30 ns tCSH SCLK falling edge to CS rising edge 30 ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tSDIS SDI setup time 5 ns tSDIH SDI hold time 5 ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODLY SCLK to SDO output delay 40 ns UART tBAUD Baud rate = 9600 ± 1% 104 µs DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tPOR POR reset delay 100 µs tRESET RESET pulse duration 100 ns tRESETWAIT Wait time after RESET pulse 10 µs AFE78101, AFE88101 SLASF21 – DECEMBER 2022 www.ti.com 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AFE78101 AFE88101 |
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