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7.5.4 Status Bits

Every response, in SPI mode and UBM, from the AFEx8101 includes a set of status bits. For SPI mode bit order,

see Section 7.5.2.1, and for UBM bit order, Section 7.5.3.1.

Table 7-9. Status Bits

STATUS BIT

DESCRIPTION

NOTES / REFERENCE

ALARM_IRQ

1h = ALARM_IRQ asserted

0h = Normal operation

From the GEN_STATUS(1) register (Table 7-33).

Also see Section 7.3.4.

CRC_ERR

(CRC enabled SPI only)

1h = CRC error detect in input frame

0h = No CRC error detected

Generated by the SPI on a frame by frame basis.

See Section 7.5.2.3.

GEN_IRQ

1h = GEN_IRQ asserted

0h = Normal Operation

From the ALARM_STATUS(1) register (Table 7-32).

Also see Section 7.3.4.

R/IRQn

(UBM only)

1h = Read request

0h = IRQ event

Generated by the UART interface on a frame by frame basis.

See Section 7.5.3.1 for details.

RESET

1h = First readback after RESET

0h = All other readbacks

From the GEN_STATUS register (Table 7-33).

Also see Section 7.4.2.

(1)

ALARM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other register. The ALARM_STATUS register

has the GEN_IRQ bit. GEN_STATUS has the ALARM_IRQ bit. This functionality enables the system microcontroller to always get full

status information by reading only one register, and thus save power.

7.5.5 Watchdog Timer

The AFEx8101 include a watchdog timer (WDT) that is used to make sure that communication between the

system controller and the device is not lost. The WDT checks that the device received a communication from

the system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The

WDT monitors both SPI and UBM communications.

The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit

for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00, then

the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too slowly

(greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in the

event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to

2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when

the timer expires.

If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window.

Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is

sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the

WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the

WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register.

The watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024).

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SLASF21 – DECEMBER 2022

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