MSP430 datasheet(79/88 Pages) TI

79 / 88 page

8.4 Power Supply Recommendations

The AFEx8101 can operate within a single-supply range of 2.7 V to 5.5 V applied to the PVDD pin. When 2.7 V

to 5.5 V is provided to PVDD, an internal LDO is enabled that drives VDD internally. VDD pin must have 1 μF to

10 μF of capacitance for operation.

The AFEx8101 can also be operated with a lower supply voltage of 1.71 V to 1.89 V applied to the PVDD pin.

When the voltage is within this lower range, the internal LDO is not operational, and the lower external supply on

the PVDD pin must be tied to the VDD pin.

The digital interface supply, IOVDD, can operate with a supply range of 1.71 V to 5.5 V.

Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the

output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily

couple into the DAC output voltage or current through various paths between the power connections and analog

output. To further reduce noise, include bulk and local decoupling capacitors. The current consumption on the

PVDD and IOVDD pins, the short-circuit current limit for the voltage output, and the current ranges for the

current output are listed in the Electrical Characteristics. The power supply must meet the requirements listed in

the Recommended Operating Conditions.

8.5 Layout

8.5.1 Layout Guidelines

To maximize the performance of the AFEx8101 in any application, follow good layout practices and proper circuit

design. The following recommendations are specific to the device:

• For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal

traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated

ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the

planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration

creates ground loops.

• IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have

at least a 1-μF decoupling capacitor used for the internal LDO, or for an external 1.8-V supply. Use a

high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low

dissipation factor.

• Place a 100-nF reference capacitor close to the VREFIO pin.

• Avoid routing switching signals near the reference input.

• Maintain proper placement for the digital and analog sections with respect to the digital and analog

components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to

minimize the interaction between analog and digital return currents.

• For designs that include protection circuits:

– Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure

that return current from high-energy transients does not cause damage to sensitive devices

– Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O

pins.

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AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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