MSP430 datasheet(49/88 Pages) TI

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7.5.3 UART

In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART

character format.

7.5.3.1 UART Break Mode (UBM)

In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device

interprets the UART break as the start to receive commands from the UART. A communication UART character

consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character

is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin

and by the AFEx8101 on the UARTOUT pin. When a valid break character is detected on UARTIN by the

AFEx8101, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and

stop bit differences between valid UBM break and communication characters must be managed by the system

microcontroller when receiving these characters from the UARTOUT pin of the AFEx8101. See Figure 6-2 for

UBM break character, communication timing details, and bit order.

AFEx8101 UART break mode communication is supported at 9600 baud.

Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The

entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be

accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and

the full register map is accessible by UBM.

A UBM data output packet is initiated by AFEx8101 on UARTOUT in two cases. See Figure 7-23 for packet

structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit

is 1, the break command is a response to the prior read request.

To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx8101 triggers a break

command followed by data on UARTOUT (see Figure 7-23).

The contents of the data are listed in order of priority below.

1. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output.

2. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output.

3. If none of the previous bits are set, then an IRQ is not generated.

A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without

the CRC (see Figure 7-20). The CRC cannot be enabled for UBM. All communication characters on the UART

bus are transmitted least significant data bit (D0) first.

Figure 7-21 shows the data structure of the UBM write command, and Figure 7-22 shows the data structure of

the UBM read command.

S = Start bit, Par = Parity bit, P = Stop bit

UART Break

UART Write Data MSB

Address

[0:6]

UART Break Write

Par

1'b0

(Write)

Data

[8:15]

Par

UART Write Data LSB

Data

[0:7]

Par

UARTIN

Figure 7-21. UARTIN Break Write Data Format

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AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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