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MSP430 датащи(PDF) 56 Page - Texas Instruments

номер детали MSP430
подробное описание детали  AFEx8101 16-Bit and 14-Bit, Low-Power DACs With Voltage Reference and Diagnostic ADC for 4-mA to 20-mA Loop-Powered Applications
PDF  88 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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MSP430 датащи(HTML) 56 Page - Texas Instruments

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7.6.1.4 DAC_CFG Register (Offset = 3h) [Reset = 0B00h]
Return to the Register Map.
Table 7-15. DAC_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
RESERVED
R/W
0h
12
PD
R/W
0h
DAC Output Buffer Power-down
DAC output set to Hi-Z in power-down.
0h = DAC output buffer enabled (default)
1h = DAC output buffer disabled
11-9
SR_CLK
R/W
5h
Slew Clock Rate
0h = 307.2 kHz
1h = 153.6 kHz
2h = 76.8 kHz
3h = 38.4 kHz
4h = 19.2 kHz
5h = 9600 Hz (default)
6h = 4800 Hz
7h = 2400 Hz
8-6
SR_STEP
R/W
4h
Slew Step Size
0h = 1 code
1h = 2 codes
2h = 4 codes
3h = 8 codes
4h = 16 codes (default)
5h = 32 codes
6h = 64 codes
7h = 128 codes
5
SR_EN
R/W
0h
Slew Enable
Enables slew on the output voltage.
0h = Disabled (default)
1h = Enabled
4
SR_MODE
R/W
0h
Slew Mode
Output slew rate mode select.
0h = Linear Slew (default)
1h = Sinusoidal Slew
3
RESERVED
R
0h
2
CLR
R/W
0h
CLEAR State
0h = Normal operation (default)
1h = Force the DAC to the CLEAR state
1
CLR_RANGE
R/W
0h
Clear Range
Sets DAC CLEAR state output range.
0h = 0.15 V to 1.25 V (default)
1h = 0.2 V to 1.0 V
0
RANGE
R/W
0h
Range
Sets DAC output range during normal operation.
0h = 0.15 V to 1.25 V (default)
1h = 0.2 V to 1.0 V
AFE78101, AFE88101
SLASF21 – DECEMBER 2022
www.ti.com
56
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: AFE78101 AFE88101



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