MSP430 datasheet(33/88 Pages) TI

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A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal

oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock

period = 13.02 μs.

Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion

rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. If PVDD ≥ 2.7 V,

then the input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If

PVDD = 1.8 V, then only the 0 V to 1.25 V range is allowed. In this case, the ADC_CFG.RANGE bit is prevented

from being set.

If any ADC configuration bits are changed, the following sequence is recommended:

1. Disable the ADC

2. Wait for ADC_BUSY to go low

3. Change the configuration

4. Restart the conversions

ADC_BUSY can be monitored in the GEN_STATUS register.

If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired

channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished

converting. This command converts all the selected channels once. To initiate another conversion of the

channels, send another TRIGGER.ADC command.

7.3.2.3 ADC Synchronization

The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is

generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the

data registers does not interfere with the conversion process, and thus provides continuous ADC operation.

In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete,

and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has

returned to the idle state.

7.3.2.4 ADC Offset Calibration

Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the

ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in

subsequent measurements.

This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset.

The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel

is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or

negative; therefore, the value is stored in 2’s complement notation.

With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from

conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to

enable the offset bypass.

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SLASF21 – DECEMBER 2022

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MSP430 датащи(PDF) 33 Page - Texas Instruments