MSP430 datasheet(25/88 Pages) TI

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7.3.1.3 DAC Transfer Function

The following equation describes the DAC transfer function, which is the relationship between internal signal

DAC_CODE and output voltage VOUT:

VOUT=DAC_CODE2N×FSR+VMIN

(1)

where

• DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code

loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1.

• N = DAC_CODE resolution in bits (16 for the AFE88101 and 14 for the AFE78101).

• FSR = VOUT full-scale range for the selected output range in Table 7-2.

• VMIN = the lowest voltage for the selected DAC output range.

Table 7-2. FSR and VMIN for all VOUT Ranges

PVDD

DAC_CFG.RANGE

VOUT RANGE

FSR

VMIN

1.8 V

0.15 V to 1.25 V

1.1 V

0.15 V

1.8 V

0.2 V to 1.0 V

0.8 V

0.2 V

≥ 2.7 V

0.3 V to 2.5 V

2.2 V

0.3 V

≥ 2.7 V

0.4 V to 2.0 V

1.6 V

0.4 V

The VOUT range for the DAC is determined by DAC_CFG.RANGE bit when not in the CLEAR state. In the

CLEAR state, the range is determined by DAC_CFG.CLR_RANGE bit.

7.3.1.4 DAC Gain and Offset Calibration

The AFEx8101 provide DAC gain and offset calibration capability to correct for end-point errors present

in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and

DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values

to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using Equation 2.

DAC_GAIN=12+GAIN2N

(2)

where

• N = DAC_GAIN resolution in bits: 16 for the AFE88101 and 14 for the AFE78101.

• GAIN is the decimal value of the DAC_GAIN register setting.

• GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE78101.

The example DAC_GAIN settings for the AFE88101 are shown in Table 7-3.

Table 7-3. DAC_GAIN Setting vs GAIN Code

DAC_GAIN

GAIN (HEX)

0.5

0x0000

1.0

0x8000

1.499985

0xFFFF

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AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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