MSP430 datasheet(41/88 Pages) TI

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7.3.4 IRQ

The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host

controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ

pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. Figure

7-15 shows the IRQ block diagram.

GEN_STATUS

ALARM_STATUS

GEN_STATUS_MASK

ALARM_STATUS_MASK

Interrupt

Generation

Maskable

Status Bits

CLK

Internal Oscillator

CLK

CONFIG.IRQ_POL

CONFIG.IRQ_LVL

XOR

IRQ Pulse

Generation

(813-ns Wide)

IRQ

Figure 7-15. IRQ Block Diagram

There are two registers that can generate interrupts: GEN_STATUS and ALARM_STATUS. Each of these

registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger

an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing

a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are

sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists.

The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable

level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal

clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition

exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register.

Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky.

CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high.

When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection.

With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to

20 ns.

Most status bits have two versions within the design. The first version is an edge event that is created when the

status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple

status events from blocking one another. The second version is the sticky version of the status bit. This signal is

set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the

status condition does not still persist. Signals GEN_IRQ and ALARM_IRQ are driven by the logical OR of the of

the status bits within the corresponding register.

If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive,

then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event

must occur after the bit has been unmasked to assert an interrupt.

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SLASF21 – DECEMBER 2022

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