MSP430 datasheet(23/88 Pages) TI

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7.3 Feature Description

7.3.1 Digital-to-Analog Converter (DAC) Overview

The AFEx8101 feature a 16

‑bit (AFE88101) or 14-bit (AFE78101) string DAC followed by an output voltage

buffer. The DAC can be configured to support two low PVDD (0.15 V to 1.25 V and 0.2 V to 1 V), or high

PVDD (0.3 V to 2.5 V and 0.4 V to 2 V) output ranges of operation depending on the PVDD supply voltage

and the DAC_CFG.RANGE bit in the device configuration register. Using a voltage-to-current converter stage,

these output voltages can be used to control a 4 mA to 20 mA loop. The narrow range corresponds to a 4-mA to

20-mA range. The full range allows for currents under and over the 4-mA to 20-mA range.

The devices continuously monitor the PVDD supply to provide proper operation based on the DAC range setting.

Table 7-1 shows the valid supply ranges and corresponding VOUT DAC voltage ranges for the AFEx8101.

Table 7-1. VOUT DAC Voltage Ranges

DAC

CONFIGURATION

SUPPLY

DAC_CFG.RANGE

NAME

VOUT DAC

VOLTAGE RANGE

PVDD

VDD

Invalid configuration

0 V ≤ PVDD < 1.71 V

0 V ≤ VDD < 1.71 V

Alarm condition(1)

0.15 V or 1.25 V(2)

Low PVDD DAC

range

1.71 V ≤ PVDD ≤ 1.89 V

1.71 V ≤ VDD ≤ 1.89 V

Full range

0.15 V to 1.25 V

Narrow range

0.2 V to 1 V

Invalid configuration

1.89 V < PVDD < 2.7 V

VDD > 1.89 V

Alarm condition(1)

0.15 V or 1.25 V(2)

High PVDD DAC

range

2.7 V ≤ PVDD ≤ 5.5 V

VDD is internally

generated

Full range

0.3 V to 2.5 V

Narrow range

0.4 V to 2 V

Invalid configuration

PVDD > 5.5 V

VDD > 1.89 V

Alarm condition(1)

0.3 V or 2.5 V(2)

(1)

See Table 7-7 for details.

(2)

See Figure 7-12 for details.

If PVDD or VDD fall outside the specified threshold values associated with the supply configuration during

operation, an alarm is generated and the DAC output is set according to the ALARM_ACTION setting.

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AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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