MSP430 datasheet(22/88 Pages) TI

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7 Detailed Description

7.1 Overview

The AFEx8101 feature a 16-bit (AFE88101) or 14

‑bit (AFE78101) string DAC with voltage output buffer. Both

devices are capable of operating from supplies as low as 1.71 V at very low power, and are designed for 4-mA to

20-mA, loop-powered applications. The AFEx8101 have two different DAC output voltage ranges depending on

supply voltage, and two other ranges depending on configuration. The DAC has calibration registers for setting

gain and offset values for adjusting the DAC outputs. The DAC also has different output slewing modes that

allow for a programmable linear slew and a sinusoidal shaped output slew.

The AFEx8101 also feature a 12

‑bit SAR ADC that can be multiplexed to measure different inputs, including

external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making

direct-mode measurements with on-demand conversions or auto-mode measurements through continuous

conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with

fault detection and alarm actions.

Device communication and programming are done through an SPI or through the UART break mode (UBM).

With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally,

communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes

unresponsive to periodic communication.

The AFEx8101 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator.

Throughout this data sheet, register and bit names are combined with a period to use the following format:

<register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR.

7.2 Functional Block Diagram

MUX

12-Bit ADC

MUX

Internal

Diagnostics

Temperature

Sensor

AIN0

POL_SEL/AIN1

16-/14-Bit

DAC

VOUT

Alarm

Diagnostics

Alarm

Responses

User

Calibration

Slew-Rate

Control

DAC Data

Watchdog

Timer

CRC Frame

Error Check

ALARM

Control Logic

SDI

SDO

SCLK

SCLR

UARTIN

UARTOUT

PVDD

VDD

GND

Internal

Reference

VREFIO

REF_EN

REF_GND

IOVDD

RESET

Internal

Oscillator

CLK_OUT

IRQ (UARTOUT or SDO)

Output Buffer

Range Setting

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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