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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSP430 датащи(PDF) 65 Page - Texas Instruments |
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MSP430 датащи(HTML) 65 Page - Texas Instruments |
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65 / 88 page  7.6.1.21 ALARM_STATUS Register (Offset = 20h) [Reset = 0200h] Return to the Register Map. Table 7-32. ALARM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register. 0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 RESERVED R 0h 13 SD_FLT R 0h Self Diagnostic (SD) Fault 0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ. 0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault Counter If counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ. 0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist. 0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist. 0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C www.ti.com AFE78101, AFE88101 SLASF21 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: AFE78101 AFE88101 |
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