MSP430 datasheet(42/88 Pages) TI

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7.3.5 Internal Reference

The AFEx8101 family of devices includes a 1.25-V precision band-gap reference. The internal reference is

externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor

between the reference output and GND.

The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables

the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference,

and the device expects to have 1.25 V from external VREF at the VREFIO pin.

An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting

in the ALARM_ACT register (10h).

7.3.6 Integrated Precision Oscillator

The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5%

tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up,

the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the

ADC data output is accurate to the electrical specifications provided in Section 6.

7.3.7 One-Time Programmable (OTP) Memory

One-time programmable (OTP) memory in the device is used to store the device trim settings and is not

accessible to users. The OTP memory data are loaded to the memory at power up. The OTP memory CRC

is performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate

a reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit

controls whether the OTP memory data are reloaded with a software reset.

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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MSP430 датащи(PDF) 42 Page - Texas Instruments