CS4210 datasheet(17/102 Pages) NSC

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Operational Description (Continued)

3.2.3.3

Isoch Tx and Rx Context Interrupts

Each of the eight implemented isochronous transmit and

each of the eight implemented isochronous receive con-

texts can generate an interrupt. Software can enable inter-

rupts on a per-context basis by setting the corresponding

IsochTxnContextIntMask or IsochRxnContextIntMask bit to

one. To efficiently handle interrupts which could conceiv-

ably be generated from eight different contexts in close

proximity to one another, there is a single bit for all IT DMA

contexts and another for all IR DMA contexts in the

CS4210 IntEvent register. These bits signify that at least

one but potentially several IT or IR DMA contexts

attempted to generate an interrupt. Software can read the

isochTxIntEvent register to find out which isochronous

transmit context(s) are involved. Software can read the Iso-

chRxIntEvent register to find out which isochronous receive

context(s) are involved.

Table 3-4 shows a map of the IsochTx/Rx Context Interrupt

Event and Mask Set/Clear registers. Refer to Section

4.4.16.4 on page 73 through Section 4.4.16.7 on page 74

for further register information.

The number of supported isochronous DMA contexts var-

ies for 1394 OHCI implementations from a minimum of four

to a maximum of 32. Software can determine the number

supported

DMA

contexts

writing

FFFF_FFFFh to IsochTxIntMask register for IT and Isoch-

RxIntMask register for IR, and then reading it back. Bits

returned as 1’s indicate supported contexts, and bits

returned as 0’s indicate unsupported/unimplemented con-

texts.

Table 3-4. IsochTx and IsochRx Context Interrupt Related Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

BAR0+Offset 90h

IsochTxIntEvent Set Register

BAR0+Offset 94h

IsochTxIntEvent Clear Register

RSVD

BAR0+Offset 98h

IsochTxIntMask Set Register

BAR0+Offset 9Ch

IsochTxIntMask Clear Register

RSVD

BAR0+Offset A0h

IsochRxIntEvent Set Register

BAR0+Offset A4h

IsochRxIntEvent Clear Register

RSVD

BAR0+Offset A8h

IsochRxIntMaskSet Register

BAR0+Offset ACh

IsochRxIntMaskClear Register

RSVD

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