CS4210 datasheet(75/102 Pages) NSC

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4.4.17 Fairness Control Register

This register (Table 4-32) provides a mechanism by which

software can direct the CS4210 to transmit multiple asyn-

chronous request packets during a fairness interval as

specified in P1394a specification.

4.4.18 LinkControl Register

This register (Table 4-33) provides the control flags that

enable and configure the link core protocol and controls for

the

receiver

and cycle

timer.

This

set

(BAR0+Offset E0h) and clear (BAR0+Offset E4h). On

read, both addresses return LinkControl.

Table 4-32. BAR0+Offset DCh: Fairness Control Register

Bit

Name

Access

Reset

Description

31:8

RSVD

Reserved

7:0

pri_req

HW =

Undef

SW/Bus

=N/A

Priority Arbitration Request: This field specifies the maximum number of

priority arbitration requests for asynchronous request packets that the link is

permitted to make to the CS4103 during a fairness interval. A pri_req value

of 00h is equivalent to the behavior specified by the IEEE 1394-1995 speci-

fication.

Table 4-33. BAR0+Offset E0h (Set) and E4h (Clear): LinkControl Register

Bit

Name

Access

Reset

Description

32:21

RSVD

Reserved

cycleSource

RSC

or R

HW = 0

SW = No

Change

Cycle Source: When one, the cycle timer uses an external source to deter-

mine when to increment cycleCount (BAR0+Offset F0h[24:12]). When

cycleCount is incremented, cycleOffset (BAR0+Offset F0h[11:0]) is reset to

0. If cycleOffset reaches 3071 before an external event occurs, it remains at

3071 until the external signal is received and is then reset to 0. When the

cycleSource bit is zero, the CS4210 rolls the cycle timer over when the

timer reaches 3072 cycles of the 24.576 MHz clock (8 kHz). CycleSource

has an effect only when cycleMaster (bit 21) is enabled. A hardware reset

clears to 0. A software reset has no effect.

cycleMaster

RSCU

Undef

Cycle Master: When one and the CS4103 has notified the CS4210 that it is

root, the CS4210 generates a cycle start packet every time the cycle timer

rolls over, based on the setting of the cycleSource bit (bit 22). When zero,

the CS4210 accepts received cycle start packets to maintain synchroniza-

tion with the node which is sending them. This bit is automatically zeroed

when the IntEvent.cycleTooLong event occurs and cannot be set until the

IntEvent.cycleTooLong bit (BAR0+Offset 80h[25]) is cleared.

cycleTimerEnable

RSC

Undef

Cycle Timer Enable: When one, the cycle timer offset counts cycles of the

24.576 MHz clock and rolls over at the appropriate time based on the set-

tings of the above bits. When zero, the cycle timer offset will not count.

19:11

RSVD

Reserved

rcvPhyPkt

RSC

Undef

Receive Physical Layer Packet: When one, the receiver accepts incoming

CS4103 packets into the AR request context if the AR request context is

enabled. This does not control either the receipt of self-identification pack-

ets during the Self-ID phase of bus initialization or the queuing of synthe-

sized bus reset packets in the ARDMA Request Context buffer (see Section

3.8 "Bus Resets" on page 30). This does control receipt of any self- identifi-

cation packets received outside of the Self-ID phase of bus initialization.

rcvSelfID

RSC

Undef

Receive Self-ID: When one, the receiver accepts incoming self-identifica-

tion packets. Before setting this bit to one, software must ensure that the

selfIDBufferPtr register bits (BAR0+Offset 64h[31:11]) contains a valid

address.

8:0

RSVD

Reserved

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