CS4210 datasheet(84/102 Pages) NSC

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4.4.26 Isochronous Transmit

Each isochronous transmit context consists of two regis-

ters: CommandPtr and ContextControl. CommandPtr is

used by software to tell the ITDMA controller where the

DMA context program begins. IsochTxContextControl is

used by software to control the context’s behavior, and is

used by hardware to indicate current status.

The CS4210 has eight isochronous transmit contexts.

These registers are repeated at offsets of 10h times the

context number. Table 4-49 is a map providing the offset

addresses for the isochronous transmit ContextControl and

CommandPtr registers.

4.4.26.1

Isoch Transmit Context Control Register

The IsochTxContextControl Set/Clear registers (Table 4-50

on page 85) contain bits that control options, operational

state, and status for the ITDMA contexts. Software can set

selected bits by writing ones to the corresponding bits in

the ContextControl Set register. Software can clear

selected bits by writing ones to the corresponding bits in

the ContextControl Clear register. It is not possible for soft-

ware to set some bits and clear others in an atomic opera-

tion. A read from either register returns the same value.

In addition to the standard ContextControl fields, it includes

a mechanism for starting transmit at a specified cycle time.

The cycleMatch field is used to start an ITDMA context pro-

gram on a specified cycle. Software enables matching by

setting the cycleMatchEnable bit. When the low order two

bits of the bus IsochCycleTimer.cycleSeconds and Isoch-

CycleTimer.cycleCount (BAR0+Offset F0h) value matches

the cycleMatch value, hardware clears the cycleMatchEn-

able bit to 0, sets the ContextControl.active bit to 1, and

begins executing descriptor blocks for the context. The

transition of an ITDMA context to the active state from the

not-active state is dependent upon the values of the run

and cycleMatchEnable bits.

If runtransitions to1whencycleMatchEnableis0,thenthe

context becomes active (active = 1).

If both run and cycleMatchEnable are set to 1, then the

context becomes active when the low order two bits of the

bus IsochCycleTimer.cycleSeconds and 13-bit IsochCy-

cleTimer. cycleCount values match the 15-bit cycleMatch

value.

If both run and cycleMatchEnable are set to 1, and cycleM-

atchEnable is subsequently cleared, the context becomes

active.

If both run and active are 1 (the context is active), and then

cycleMatchEnable is set to 1, this results in unspecified

behavior.

Due to software latencies, software attempts to manage

the startup of a context too close to the current time may

not be effective.

In addition, the usability of cycleMatchEnable for IT con-

texts is impacted by the cycleInconsistent interrupt. Refer

to Section 3.2.3.3 "Isoch Tx and Rx Context Interrupts" on

page 17 for more information.

Table 4-49. IsochTx Register Address Map

BAR0+Offset

Name

200h

IsochTx0ContextControl Set Register

204h

IsochTx0ContextControl Clear Register

208h

Reserved

20Ch

IsochTx0CommandPtr Register

210h

IsochTx1ContextControl Set Register

214h

IsochTx1ContextControl Clear Register

218h

Reserved

21Ch

IsochTx1CommandPtr Register

220h

IsochTx2ContextControl Set Register

224h

IsochTx2ContextControl Clear Register

228h

Reserved

22Ch

IsochTx2CommandPtr Register

230h

IsochTx3ContextControl Set Register

234h

IsochTx3ContextControl Clear Register

238h

Reserved

23Ch

IsochTx3CommandPtr Register

240h

IsochTx4ContextControl Set Register

244h

IsochTx4ContextControl Clear Register

248h

Reserved

24Ch

IsochTx4CommandPtr Register

250h

IsochTx5ContextControl Set Register

254h

IsochTx5ContextControl Clear Register

258h

Reserved

25Ch

IsochTx5CommandPtr Register

260h

IsochTx6ContextControl Set Register

264h

IsochTx6ContextControl Clear Register

268h

Reserved

26Ch

IsochTx6CommandPtr Register

270h

IsochTx7ContextControl Set Register

274h

IsochTx7ContextControl Clear Register

278h

Reserved

27Ch

IsochTx7CommandPtr Register

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