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4.4.27.2 Isoch Receive Command Pointer Register

The CommandPtr register (Table 4-54) specifies the

address of the context program which is executed when a

DMA context is started. All descriptors are 16-byte aligned,

so the four least-significant bits of any descriptor address

must be zero. The four least-significant bits of the Com-

mand Pointer register are used to encode a Z value that

indicates how many physically contiguous descriptors are

pointed to by descriptorAddress. In buffer-fill mode, Z is

either one or zero. In packet-per-buffer mode, Z is from

zero to eight.

These registers are repeated at offsets of 20h times the

context number (see Table 4-52 for offset address assign-

ment).

4.4.27.3 Isoch Receive Context Match Register

The ContextMatch register (Table 4-55) is used to start a

context running on a specified cycle number, to filter incom-

ing isochronous packets based on tag values and to wait

for packets with a specified sync value. All packets are

checked for a matching tag value, and a compare on sync

is only performed when the descriptor’s w field is set to 11.

See 1394 OHCI spec data fields for proper usage of the w

field. This register should only be written when Context-

Control.active is 0, otherwise unspecified behavior results.

These registers are repeated at offsets of 20h times the

context number (see Table 4-52 for offset address assign-

ment).

Table 4-54. IsochRxnCommandPtr Register

Bit

Name

Access

Reset

Description

31:4

descriptorAddress

RWU

Undef

Descriptor Address: Contains the upper 28 bits of the address of a 16-

byte aligned descriptor block. See Section 3.3.2.5 "CommandPtr" on page

22 for details.

3:0

RWU

Undef

Z: Indicates the number of contiguous 16-byte aligned blocks at the

address pointed to by descriptorAddress. If Z is 0, it indicates that the

descriptorAddress is not valid.

Table 4-55. IsochRxnContextMatch Register

Bit

Name

Access

Reset

Description

tag3

Undef

Tag 3: If set, this context matches on isochronous receive packets with a

tag field of 11h.

tag2

Undef

Tag 2: If set, this context matches on isochronous receive packets with a

tag field of 10h.

tag1

Undef

Tag 1: If set, this context matches on isochronous receive packets with a

tag field of 01h.

tag0

Undef

Tag 0: If set, this context matches on isochronous receive packets with a

tag field of 00h.

RSVD

Reserved

26:12

cycleMatch

Undef

Cycle Match: Contains a 15-bit value, corresponding to the low order two

bits of cycleSeconds and the 13-bit cycleCount field in the cycleStart

packet. If cycleMatchEnable (bit 29 of corresponding IsochRxnContextCon-

trol register) is set, then this IRDMA context becomes enabled for receives

when the two low order bits of the bus cycleTime.cycleSeconds and

cycleTime.cycleCount (BAR0+Offset F0h) values equal the cycleMatch

value.

11:8

sync

Undef

Synchronous: This field contains the 4-bit field which is compared to the

sync field of each isochronous packet for this channel when the command

descriptor’s w field is set to 11h.

7RSVD

Reserved

tag1SynFilter

Undef

Tag 1 Synchronous Filter: If set and the contextMatch.tag1 bit is set, then

packets with tag 01h shall only be accepted into the context if the two most-

significant bits of the packet’s sync field are 00h. Packets with tag values

other than 01h shall be filtered according to the tag0, tag2 and tag3 bits

above with no additional restrictions.

If clear, this context matches on isochronous receive packets as specified in

the tag[0:3] bits above with no additional restrictions.

5:0

channelNum

Undef

Channel Number: This 6-bit field indicates the isochronous channel num-

ber for which this IRDMA context accepts packets.

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