CS4210 datasheet(30/102 Pages) NSC

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Operational Description (Continued)

3.8

BUS RESETS

When a 1394 bus reset occurs, certain actions must be

taken by software for proper operation of the DMA con-

texts. These actions and the behavior of the CS4210 are

described in the following subsections.

3.8.1

Asynchronous Transmit

Upon detection of a bus reset, the CS4210 ceases trans-

mission of asynchronous transmit packets. When this

occurs there are two possibilities for AT packets that are left

in the FIFO.

• Case 1 is when a bus reset occurs after the packet was

transmitted but before an ack was received. For this

category, the link side of the CS4210 returns

evt_missing_ack.

• Case 2 is when a bus reset occurs after the packet is

placed in the FIFO but before it is transmitted. For this

category, the link side of the CS4210 returns

evt_flushed.

When each context becomes stable (all data transfers have

been halted and status writes have been completed), the

CS4210 clears the corresponding ContextControl.active

bit.

When a bus reset occurs, the link side flushes the asyn-

chronous transmit FIFO(s) until the IntEvent.busReset con-

dition

cleared.

Software

must

make

sure

that

IntEvent.busReset is not cleared until:

software has cleared the ContextControl.run bits for

both Asynchronous Transmit contexts, and

both Asynchronous Transmit contexts have acqui-

esced and both ContextControl.active fields are zero.

This is to ensure that all queued asynchronous pack-

ets (with potentially stale node numbers) are flushed.

Once the contexts are no longer active, software may clear

the busReset interrupt condition, and hardware stops flush-

ing the asynchronous transmit FIFO(s). Before setting Con-

textControl.run for either context following a bus reset,

software must ensure that NodeID.iDValid is set and that

NodeID.nodeNumber (Section 4.4.19 "Node ID and Status

3.8.2

Asynchronous Receive

To assist software in determining which asynchronous

request packets arrived before and after a bus reset, this is

necessary since node numbers may have changed, the

CS4210 inserts a synthesized CS4103 packet into the AR

DMA Request Context buffer (if active) as soon as a bus

reset condition is detected. The format of the packet can be

found in the 1394 OHCI specification.

Software can distinguish the bus-reset packet from authen-

tic CS4103 packets by the value of eventCode which is set

to evt_bus_reset. Software can further interpret and coordi-

nate received asynchronous packets across multiple bus

resets by using the selfIDGeneration number provided in

the bus-reset packet. Since the bus-reset packet is fabri-

cated when a bus reset is initially detected, the selfIDGen-

eration number is for the new (not previous) generation and

is the same as the selfIDGeneration number in the SelfID-

Count register as well as in the selfID buffer. If more than

one bus reset has occurred without any intervening pack-

ets, then only the “last” one is required to result in a synthe-

sized bus-reset packet. If the input FIFO is full when a bus

reset occurs, the link side of the FIFO inserts the bus-reset

packet when space becomes available. If the AR DMA

request context does not have enough buffer space for the

bus-reset packet, the packet is synthesized once buffer

space

becomes

available.

The

bus

reset

interrupt

(IntEvent.busReset) is independent on the time when this

packet goes from the FIFO into a host buffer. This interrupt

shall occur as soon as possible after a bus reset has been

detected. The bus-reset packet is no different from any

other packet going into the AR Request buffer in that

IntEvent.RQPkt is generated like it is for other packets.

3.8.3

Isochronous Transmit and Receive

Bus reset does not affect isochronous contexts.

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