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CS4210 датащи(PDF) 97 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали CS4210
подробное описание детали  IEEE 1394 OHCI Controller
PDF  102 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
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CS4210 датащи(HTML) 97 Page - National Semiconductor (TI)

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Revision 1.0
97
www.national.com
5.0
Electrical Specifications
This section provides information on NAND tree test mode,
absolute maximum ratings, recommended operating condi-
tions, and DC/AC characteristics for the Geode CS4210.
5.1
NAND TREE TEST MODE
The NAND tree test mode is used to test input and bidirec-
tional pins which are part of the NAND tree chain. After
power is applied to the CS4210, pin 7 (TESTO) is the out-
put of the NAND tree. To test the NAND tree, all inputs in
Table 5-1 are held low and then a high is successively
applied to the inputs in the order listed in Table 5-1. The
TESTO output will toggle on each input change as shown
in Figure 5-1.
The TESTO pin will continue to output the result of the
NAND tree during normal operation. If this is undesirable,
nscControl.testOutSel (BAR1+Offset 00h[19]) can be set
and TESTO will reflect the BIST output which does not tog-
gle during normal operation. The nscControl register is
loaded via the serial EEPROM upon power up, so nscCon-
trol.testOutSel can be set as the default if desired.
Table 5-1. NAND Tree Test Mode Pins
Signal Name
Pin No.
LNKON
98
SCLK
95
CTL0
93
CTL1
92
DATA0
90
DATA1
89
DATA2
88
DATA3
86
DATA4
85
DATA5
84
DATA6
82
DATA7
81
DIRECT
79
CCLKI
78
TESTEN#
76
AD0
74
AD1
73
AD2
72
AD3
71
AD4
69
AD5
68
AD6
67
AD7
66
C/BE0#
65
AD8
64
AD9
62
AD10
61
AD11
59
AD12
58
AD13
57
AD14
56
AD15
54
C/BE1#
53
PAR
52
Signal Name
Pin No.
SERR#
51
PERR#
49
STOP#
48
DEVSEL#
47
TRDY#
45
IRDY#
44
FRAME#
43
C/BE2#
41
AD16
40
AD17
38
AD18
37
AD19
36
AD20
34
AD21
33
AD22
32
AD23
31
IDSEL
29
Signal Name
Pin No.
C/BE3#
28
AD24
27
AD25
26
AD26
25
AD27
23
AD28
22
AD29
21
AD30
19
AD31
18
PME#
17
PGNT#
14
PCLK
12
RST#
10
EEDATA
5
EECLK
4
Signal Name
Pin No.
Figure 5-1. NAND Tree Output Waveform
TESTO
LNKON
SCLK
CTL0
CTL1
DATA0
100 ns
:::
:::
:::
EECLK
Note:
The following pins are not in the NAND tree: CMC, CMCL, INTA#, PREQ#, CCLKO, LREQ, LPS, and all supplies.



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