CS4210 datasheet(94/102 Pages) NSC

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4.5.4

nscRAMBist

ThenscRAMBist register (Table4-61) is used to test the

FIFOs implemented in SRAM. The bistGo bit is set and the

bistFail and bistPass bits are polled until one is set, indicat-

ing pass or fail. The CS4210 must be reset before normal

operation can resume.

4.5.5

nscCmcControl

The nscCmcControl register (Table 4-62) controls the state

of theCMC andCMCLpins. Thesepinsare intended for

use with Contender pins on 1394-1995 PHY devices. This

feature is not used on the CS4103.

4.5.6

nscTxThreshold

The nscTxThreshold register (Table 4-63) is used to control

the point at which the transmit FIFOs start sending data

over the 1394 bus. Lowering the threshold value causes

smaller packets to be sent. This register can only be written

to when the nscControl.wpDisable bit (BAR1+Offset

00h[3]) is set. This register may be configured via the serial

EEPROM interface (if EEPROM is present).

4.5.7

nscSubSystem

The nscSubSystem register (Table 4-64) is used to config-

ure the subsystem vendor ID and the subsystem device ID

values in the PCI configuration space. This register can

only be written to when the nscControl.wpDisable bit

(BAR1+Offset 00h[3]) is set. This register may be config-

ured via the serial EEPROM interface (if EEPROM is

present).

Table 4-61. BAR1+Offset 14h: nscRAMBist Register

Bit

Name

Access

Reset

Description

31:10

RSVD

Reserved

bistFail

Undef

Built-in Self-Test Fail: Set to 1 when RAM BIST has failed.

bistPass

Undef

Built-in Self-Test Pass: Set to 1 when RAM BIST has passed.

7:1

RSVD

Reserved

bistGo

Undef

Built-in Self-Test Go: RAM BIST is started by writing a 1 to this bit.

Table 4-62. BAR1+Offset 18h: nscCmcControl Register

Bit

Name

Access

Reset

Description

31:2

RSVD

Reserved

1CMCL

Contender Master Control Link Enabled: This bit is ANDed with HCCon-

trol.LinkEnable (BAR0+Offset 50h[17]) and the result is reflected on pin 3.

0CMC

Contender Master Control: Selects polarity of CMC output. This bit is

directly reflected on pin 2. 0 = Low; 1 = High.

Table 4-63. BAR1+Offset 20h: nscTxThreshold Register

Bit

Name

Access

Reset

Description

31:16

isochTxThrsh

01FEh

Isochronous Transmit Threshold: FIFO threshold value when transmit-

ting isochronous packets. D[18:16] are hardwired to 110 and D[31:25] are

hardwired to 00h.

15:0

asyncTxThrsh

01FEh

Asynchronous Transmit Threshold: FIFO threshold value when transmit-

ting asynchronous packets. D[2:0] are hardwired to 110 and the D[15:9] are

hardwired to 00h.

Table 4-64. BAR1+Offset 24h: nscSubSystem Register

Bit

Name

Access

Reset

Description

31:16

deviceID

0000h

Device ID: PCI configuration subsystem device ID.

15:0

vendorID

0000h

Vendor ID: PCI configuration subsystem vendor ID.

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